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OKI Semiconductor
ML2252/54-XXX, ML22Q54
2-Channel Mixing Oki ADPCM Algorithm-Based Speech Synthesis LSI
FEDL2250DIGEST-01
Issue Date: Oct. 15, 2002
This document contains minimum specifications. For full specifications, please contact your nearest Oki office or representative.
GENERAL DESCRIPTION
The ML2250 family is a 2-channel mixing speech synthesis device with an on-chip voice data (i.e., phrases) storing mask ROM and a flash memory. Besides playing the built-in voice data, this device can output voice data that is input from outside the device. This ML2250 family allows to select the playback method from the 8-bit PCM, non-linear 8-bit PCM, 16-bit PCM, 2-bit ADPCM2, and 4-bit ADPCM2 algorithms. And the sound volume is adjustable as well. The ML2250 family incorporates a 14-bit D/A converter, low-pass filter, and 1-bit DAC (PWM output). It is easy to configure a speech synthesizer by externally connecting a power amplifier and a CPU to the ML2250 family. The ML2250 family line-up includes 2 types of products: with on-chip mask ROM, and with on-chip flash memory. * ML2252/54-XXX This is a CMOS single chip speech synthesis device with an on-chip mask ROM. Products with 2 types of mask ROMs are available in the ML2250 family depending upon the total playback time length. * ML22Q54 The ML22Q54 is a speech synthesis device with a 4-Mbit flash memory built in. The voice data can be easily written to the flash memory using a special tool. The on-chip flash memory product is suitable for the diversified low volume production or short delivery time applications that the on-chip mask ROM product cannot support. The ML22Q54 is most suitable for evaluation because the circuit configuration is the same as the on-chip mask ROM product. A combination of fixed and variable messages can be written because it is easy to write to the built-in flash memory. It is also possible to store and read data, other than voice, to/from an area in the flash memory not used as voice data.
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Table below summarizes the points of difference between the ML2250 family and currently manufactured products with a ROM built in.
ML2250 family Interface Parallel or serial 2-bit ADPCM2 4-bit ADPCM2 Playback method 8-bit PCM 8-bit non-linear PCM 16-bit PCM Max. number of phrases Sampling frequency (kHz) 256 4.0/5.3/6.4/8.0/10.7/ 12.8/16.0/21.3/25.6/ 32.0/42.7/48.0 4.096 MHz 1-bit DAC PWM Voltage type: 14 bits FIR type interpolation filter 2 channels Both 2 channels without user definable phrase restrictions 29 steps (-2 dB/-5 dB steps) No limit Each channel independent 0 (Note) External data input possible 127 4.0/5.3/6.4/8.0/10.7/ 12.8/16.0/32.0 256 kHz (CR oscillation) 4.096 MHz (XT) D/A converter Low-pass filter Number of channels Voltage type: 12 bits Secondary comb filter 2 channels Can edit 8 phrases (1 channel only) 4 steps (-6 dB steps) 4 types Simultaneous channels 1 and 2 4 sampling cycles 63 4.0/5.3/6.4/8.0/10.7/ 12.8/16.0 256 kHz (CR oscillation) 4.096 MHz (XT) Current type: 10 bits Primary comb filter 1 channel Current type: 12 bits Secondary comb filter 1 channel 247 4.0/5.3/6.4/8.0/10.7/ 12.8/16.0 4-bit ADPCM 8-bit PCM 8-bit PCM 8-bit non-linear PCM 4-bit ADPCM 8-bit PCM 8-bit non-linear PCM MSM6650 family Parallel, serial or stand-alone MSM9800 family Parallel or stand-alone ML2210 family Serial
Clock frequency
4.096 MHz
Phrase control table
Can edit 8 phrases
None
Volume adjustment Repeat function STOP Seam silence interval in continuous playback Others
Set at VREF. None Available
Set at VREF. None Available
3 sampling cycles
4 sampling cycles
--
--
--
Note: Continuous playback shown in the figure below is possible.
1 phrase 1 phrase 1 phrase 1 phrase
Conventional
ML2250 family Silence interval No silence interval
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FEATURES
Type ML2252 ML2254 ML22Q54 ROM capacity 1 Mbit 4 Mbit 4 Mbit Maximum playback time length (sec) (In 4-bit ADPCM2) FSAM = 4.0 kHz FSAM = 6.4 kHz FSAM = 8.0 kHz FSAM = 16 kHz FSAM = 32 kHz 64.5 261.1 261.1 40.3 163.2 163.2 32.2 130.5 130.5 16.1 65.2 65.2 8.0 32.6 32.6
* Non-linear 8-bit PCM, 8-bit PCM, 16-bit PCM, 2-bit ADPCM2, and 4-bit ADPCM2 algorithms * Serial input/parallel input selectable * Phrase control table function i.e., user definable phrase control table function * 2 channels mixing function * Master clock frequency: 4.096 MHz * Sampling frequency: 4.0 kHz, 5.3 kHz, 6.4 kHz, 8.0 kHz, 10.7 kHz, 12.8 kHz, 16.0 kHz, 21.3 kHz, 25.6 kHz, 32.0 kHz, 42.7 kHz, 48 kHz * Maximum number of phrases: 256 phrases * Sound volume adjustment function built in (2 sounds independently adjustable in 29 steps) * External voice data can be input * 1-bit D/A converter, and14-bit D/A converter built in * Built-in low-pass filter: Digital filter * Package: 44-pin plastic QFP (QFP44-P-910-0.80-2K) (ML2252-XXXGA/ML2254-XXXGA/ML22Q54GA-MC)
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BLOCK DIAGRAM
OKI Semiconductor
NCR1/NDR NCR2/DL BUSY1 BUSY2/ERR SERIAL D7/DI D6/SCK D5/DO D4 D3 D2 D1 D0 WR CS DW RD XT XT
16bit(ML2252) 18bit(ML2254) Multiplexer
1Mbit(ML2252) 4Mbit(ML2254) ROM
16
2bit ADPCM2 /4bit ADPCM2 Synthesizer
16bit(ML2252) 18bit(ML2254) Address Controller CPU Interface
Phrase Control Table
8bit PCM 16bit PCM Synthesizer & 2ch Mix
Loop Volume Phrase Address Register
Digital Filter
Command Register
1bit DAC
14bit DAC
OSC
Timing Controller
OPTANA
ML2252/54-XXX, ML22Q54
AVDD AGND RESET
FEDL2250DIGEST-01
TEST
TESTO1
TESTO2
DVDD DGND OUT(+) OUT(-) /DAO /AOUT
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ML22Q54
OKI Semiconductor
NCR1/NDR NCR2/DL BUSY1 BUSY2/ERR SERIAL D7/DI D6/SCK D5/DO D4 D3 D2 D1 D0 WR CS DW RD RD/BY
18bit Multiplexer
4Mbit Flash ROM
16
2bit ADPCM2 /4bit ADPCM2 Synthesizer
18bit Address Controller CPU Interface
Phrase Control Table
8bit PCM 16bit PCM Synthesizer & 2ch Mix
Loop Volume Command Controller
Digital Filter
1bit DAC
14bit DAC
XT XT
OSC
Timing Controller
OPTANA
ML2252/54-XXX, ML22Q54
AVDD AGND RESET
FEDL2250DIGEST-01
DVDD
DGND
TEST
TESTO
OUT(+) OUT(-) /DAO /AOUT
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PIN CONFIGURATION (TOP VIEW)
ML2252/54-XXX 44-pin plastic QFP
NC BUSY2/ERR WR NC DVDD DGND NC OPTANA CS NC NC 44 43 42 41 40 39 38 37 36 35 34
NC 1 DW 2 BUSY1 3 NCR2/DL 4 NCR1/NDR 5 RD 6 TESTO1 7 TESTO2 8 RESET 9 TEST 10 NC 11 12 13 14 15 16 17 18 19 20 21 22
33 32 31 30 29 28 27 26 25 24 23
NC SERIAL DGND AVDD OUT(-)/AOUT OUT(+)/DAO AGND D7/DI NC D6/SCK D5/DO
NC DVDD XT XT D0 DGND D1 D2 D3 D4 NC NC: No Connection
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ML2252/54-XXX, ML22Q54
ML22Q54 44-pin plastic QFP
NC BUSY2/ERR WR NC DVDD DGND NC OPTANA CS NC NC NC 1 DW 2 BUSY1 3 NCR2/DL 4 NCR1/NDR 5 RD 6 TESTO 7 RD/BY 8 RESET 9 TEST 10 NC 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34
33 32 31 30 29 28 27 26 25 24 23
NC SERIAL DGND AVDD OUT(-)/AOUT OUT(+)/DAO AGND D7/DI NC D6/SCK D5/DO
NC DVDD XT XT D0 DGND D1 D2 D3 D4 NC NC: No Connection
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PIN DESCRIPTIONS-1
ML2252/54-XXX Common Pins 44-pin plastic QFP
Pin Symbol Type Description When using the built-in ROM for voice output, this pin outputs "L" level while channel 2 side processes a command and while plays back voice. Works as ERR pin when using the EXT command for voice output. If an abnormality occurred in the transfer of data, the pin will output "L" level and the voice output may become noisy. "H" level at power on. Outputs "L" level while the channel 1 side processes a command and plays back voice. "H" level at power on. The command input of channel 2 side is valid at "H" level when using the built-in ROM for voice output. Works as DL pin when using EXT command for the voice output. This pin outputs the signal that captures voice data to inside. The data is captured inside on the rising edge of DL. "H" level at power on. The command input of channel 1 side is valid at "H" level when using the built-in ROM for voice output. Works as NDR pin when using EXT command for the voice output. The voice data input is valid at "H" level. "H" level at power on. At "L" level input, the device enters the initial state; the oscillation stops, and AOUT output and DAQ output are GND level at this time. Test pin for the device. Input "L" level to this pin. This pin has a pull-down resistor built in. Wired to a crystal or ceramic oscillator. A feedback resistor of around 1 M is built in between this XT pin and XT pin (pin 15). When using an external clock, input the clock from this pin. Wired to a ceramic or crystal oscillator. When using an external clock, keep this pin open. CPU interface data bus pins in the parallel input interface. Channel status output pins at RD pin = "L" level. In the serial input interface, keep these pins at "L" level. CPU interface data bus pin in the parallel input interface. When RD pin is at "L" level, this pin D4 usually outputs "L" level. In the serial input interface, keep this pin at "L" level. CPU interface data bus pin in the parallel input interface. When RD pin is at "L" level, this D5/DO pin usually outputs "L" level. Works as channel status output pin in the serial interface. When CS and RD pins are "L" level, the status of each channel is output serially from this D5/DO pin in synchronization with SCK clock.
43
BUSY2/ERR
O
3
BUSY1
O
4
NCR2/DL
O
5
NCR1/NDR
O
9 10
RESET
I I
TEST
14
XT
I
15
XT
O
16, 18, 19, 20
D3 D2 D1 D0 D4
I/O
21
I/O
23
D5/DO
I/O
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ML2252/54-XXX, ML22Q54
Pin
Symbol
Type
24
D6/SCK
I/O
26
D7/DI
I/O
Description CPU interface data bus pin in the parallel input interface. Usually outputs "L" level when RD = "L" level. Works as serial clock input pin in the serial input interface. When the SCK input is at "L" level on the falling edge of CS, the DI input is captured in the device on the rising edge of SCK clock. And when the SCK input is at "H" level on the falling edge of CS, the DI input is captured on the falling edge of SCK clock. CPU interface data bus pin in the parallel input interface. Usually output "L" level when RD is at "L" level. Works as serial data input pin in the serial input interface. When OPTANA pin is at "H" level, this OUT(+)/DAO pin outputs PWM (positive phase) of 1-bit DAC. When OPTANA pin is at "L" level, the OUT(+)/DAO pin outputs analog signal of 14-bit DAC. When OPTANA pin is at "H" level, this OUT(-)/AOUT pin outputs PWM (reverse phase) of 1-bit DAC. When OPTANA pin is at "L" level, the OUT(-)/AOUT pin usually outputs the analog signal of 14-bit DAC via voltage follower. CPU interface switching pin. Serial input interface at "H" level. And parallel input interface at "L" level. CPU interface chip select pin. When CS pin is at "H" level, the WR, DW, and RD signals cannot be input to the device. Analog output/PWM output select signal. When OPTANA pin is at "H" level, the PWM of 1-bit DAC outputs from OUT(+)/DAO and OUT(-)/AOUT pins. When OPTANA pin is at "L" level, the analog signal of 14-bit DAC is output from OUT(+)/DAO pin and from OUT(-)/AOUT pin via voltage follower. CPU interface write signal. When CS pin is at "H" level, the WR signal cannot be input to the device. Data write signal when using EXT command for the voice output. Set the pin to "H" level when not using EXT command. When CS pin is at "H" level, the DW signal cannot be input to the device. This pin has a pull-up resistor built in. CPU interface read signal. When CS pin is at "H" level, the RD signal cannot be input to the device. This pin has a pull-up resistor built in. Output pin for testing. Keep this pin open. Analog power supply pin. Insert a 0.1 F or larger bypass capacitor between this pin and AGND pin. Digital power supply pin. Insert a 0.1 F or larger bypass capacitor between this pin and DGND pin. Analog ground pin. Digital ground pin.
28
OUT(+)/DAO
O
29
OUT(-)/AOUT
O
32
SERIAL
CS
I
36
I
37
OPTANA
I
42
WR
I
2
DW
I
6
RD
I
7, 8
TESTO1 TESTO2 AVDD
O
30
--
13, 40 27 17, 31, 39
DVDD AGND DGND
-- -- --
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PIN DESCRIPTIONS-2
ML22Q54 Pins 44-pin plastic QFP
Pin Symbol Type Description When using the built-in ROM for voice output, this pin outputs "L" level while channel 2 side processes a command and while plays back voice. Works as ERR pin when using EXT command for the voice output. If an abnormality occurred in the transfer of data, the ERR pin outputs "L" level and the voice output may become noisy. "H" level at power on. Outputs "L" level while the channel 1 side processes a command and while plays back voice. "H" level at power on. The input command of channel 2 is valid at "H" level when using the built-in ROM for voice output. DL pin when using EXT command for the voice output. It outputs the voice data capture signal. The data is captured on the rising edge of DL. "H" level at power on. The command input of channel 1 side is valid at "H" level when using the built-in ROM for voice output. NDR pin when using EXT command for the voice output. The voice data input is effective at "H" level. "H" level at power on. When "L" level is input to this pin, the device is reset, the oscillation stops, and AOUT and DAQ outputs go into GND level. Test pin for the device. Input "L" level to this pin. This pin has a pull-down resistor built in. Wired to a crystal or ceramic oscillator. A feedback resistor of around 1 M is built in between this XT pin and XT pin (pin 15). When using an external clock, input the clock from this pin. Wired to a ceramic or crystal oscillator. When using an external clock, keep this pin open. CPU interface data bus pins in the parallel input interface. Channel status output pins when RD is at "L" level. The pins output the flash memory data when reading the built-in flash memory data. In the serial input interface, keep these pins at "L" level. CPU interface data bus pin in the parallel input interface. The pin outputs flash memory data when reading the built-in flash memory data. When RD is at "L" level other than when reading the flash memory data, this pin usually outputs "L" level. In the serial input interface, keep this pin at "L" level. CPU interface data bus pin in the parallel input interface. The pin outputs flash memory data when reading the built-in flash memory data. When RD is at "L" level other than when reading the flash memory data, this pin usually outputs "L" level. Channel status output pin in the serial input interface. When CS and RD are at "L" level, this D5/DO pin serially outputs the status of each channel in synchronization with SCK clock. When reading data of the built-in flash memory, the pin will output serially the flash memory data.
43
BUSY2/ERR
O
3
BUSY1
O
4
NCR2/DL
O
5
NCR1/NDR
O
9 10
RESET
I I
TEST
14
XT
I
15
XT
O
16, 18, 19, 20
D3 D2 D1 D0
I/O
21
D4
I/O
23
D5/DO
I/O
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ML2252/54-XXX, ML22Q54
Pin
Symbol
Type
24
D6/SCK
I/O
26
D7/DI
I/O
28
OUT(+)/DAO
O
29
OUT(-)/AOUT
O
32 36
SERIAL
CS
I I
37
OPTANA
I
42
WR
I
2
DW
I
6
RD
I
7
TESTO
O
8
RD/BY
O
Description Works as CPU interface data bus pin in parallel input interface. Works as flash memory data output pin when reading the built-in flash memory data. When RD is at "L" level other than when reading the flash memory data, this D6/SCK pin usually outputs "L" level. Works as serial clock input pin in the serial input interface. When the SCK input is at "L" level on the falling edge of CS, the DI input is captured in device on the rising edge of SCK clock. And when the SCK input is at "H" level on the falling edge of CS, the DI input is captured on the falling edge of SCK clock. Works as CPU interface data bus pin in the parallel input interface. Works as flash data output pin when reading the built-in flash memory data. When RD is at "L" level at times other than reading the flash memory data, this D7/DI pin usually outputs "L" level. Works as serial data input pin in the serial input interface. When OPTANA pin is at "H" level, this OUT(+)/DAO pin outputs PWM (positive phase) of 1-bit DAC. And when OPTANA pin is at "L" level, the OUT(+)/DAO pin outputs the 14-bit DAC analog signal. When OPTANA pin is at "H" level, this OUT(-)/AOUT pin outputs PWM (reverse phase) of 1-bit DAC. And when OPTANA pin is at "L" level, the OUT(-)/AOUT pin outputs the 14-bit DAC analog signal via voltage follower. CPU interface switching pin. At "H" level: Serial input interface. At "L" level: Parallel input interface. CPU interface chip select pin. When CS pin is at "H" level, the WR, DW, and RD signals cannot be input to the device. Analog output/PWM output select signal. At OPTANA pin = "H" level, PWM of 1-bit DAC is output from OUT(+)/DAO and OUT(-)/AOUT pins. At OPTANA pin = "L" level, 14-bit DAC analog signal is output from OUT(+)/DAO pin and 14-bit DAC analog signal is output from OUT(-)/AOUT pin via the voltage follower. CPU interface write signal. When CS pin is at "H" level, the WR signal cannot be input to the device. Data write signal at EXT command and Flash I/F command. When the EXT and Flash I/F commands are not used, keep this pin at "H" level. When CS pin is at "H" level, the DW signal cannot be input to the device. This pin has a pull-up resistor built in. CPU interface read signal. This pin is used when reading the status signal of each channel or when reading data of the built-in flash memory. When not in use, keep this pin to "H" level. This pin has a pull-up resistor built in. Output pin for testing. Keep this pin open. Output pin to indicate the automatic erase/write status of the built-in flash memory. Outputs "L" level during erase or programming cycle to indicate the busy state. Goes to "H" level at the end of the erase or programming cycle and enters into the ready state.
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Pin 30
Symbol AVDD
Type --
13, 40 27 17, 31, 39
DVDD AGND DGND
-- -- --
Description Analog power supply pin. Insert a 0.1 F or larger bypass capacitor between this pin and AGND pin. Digital power supply pin. Insert a 0.1 F or larger bypass capacitor between this pin and DGND pin. Analog ground pin. Digital ground pin.
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OKI Semiconductor
ML2252/54-XXX, ML22Q54
ABSOLUTE MAXIMUM RATINGS
(GND = 0 V) Parameter Power supply voltage Input voltage Storage temperature Symbol VDD VIN TSTG Condition Ta = 25C -- Rating -0.3 to +7.0 -0.3 to VDD +0.3 -55 to +150 Unit V V C
RECOMMENDED OPERATING CONDITIONS (3 V)
ML2252/54-XXX, ML22Q54
(GND = 0 V) Parameter Power supply voltage Operating temperature Master clock frequency Symbol VDD TOP fOSC Condition -- ML2252/54-XXX ML22Q54 -- Min. 3.5 Range 2.7 to 3.6 -40 to +85 0 to +70 Typ. 4.096 Max. 4.5 Unit V C MHz
RECOMMENDED OPERATING CONDITIONS (5 V)
ML2252/54-XXX
(GND = 0 V) Parameter Power supply voltage Operating temperature Master clock frequency Symbol VDD TOP fOSC Condition -- -- -- Min. 3.5 Range 4.5 to 5.5 -40 to +85 Typ. 4.096 Max. 4.5 Unit V C MHz
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ELECTRICAL CHARACTERISTICS
DC Characteristics (3 V) ML2252/54-XXX, ML22Q54
ML2252/54-XXX: DVDD = AVDD = 2.7 to 3.6 V, DGND = AGND = 0 V, Ta = -40 to +85C ML22Q54: DVDD = AVDD = 2.7 to 3.6 V, DGND = AGND = 0 V, Ta = 0 to +70C Parameter "H" input voltage "L" input voltage "H" output voltage "L" output voltage "H" input current 1 "H" input current 2 (Note 1) "H" input current 3 (Note 2) "L" input current 1 "L" input current 2 (Note 3) "L" input current 3 (Note 1) Playback Operating current consumption 1 Playback Operating current consumption 2 Buit-in Flash memory access Operating current consumption 1 Buit-in Flash memory access Operating current consumption 2 Standby current consumption IDD2 IDD1 Symbol VIH VIL VOH VOL IIH1 IIH2 IIH3 IIL1 IIL2 IIL3 Condition -- -- IOH = -1 mA IOL = 2 mA VIH = VDD VIH = VDD VIH = VDD Pull-down resistor built in pin VIL = GND VIL = GND Pull-up resistor built in pin VIL = GND fOSC = 4.096 MHz at no load OPTANA = "L" fOSC = 4.096 MHz at no load OPTANA = "H" fOSC = 4.096 MHz at no load IDD2 Read Operation (ML22Q54) fOSC = 4.096 MHz at no load IDD2 Write and Erase Operation (ML22Q54) Ta = -40 to +70C IDDS Ta = -40 to +85C Ta = 0 to +70C (ML22Q54) -- -- -- -- -- -- 15 50 55
A A A
Min. 0.86 x VDD -- VDD -0.4 -- -- 0.3 8 -10 -120 -15
Typ. -- -- -- -- -- 2.0 40 -- -40 -2.0
Max. -- 0.14 x VDD -- 0.4 10 15 130 -- -10 -0.3
Unit V V V V
A A A A A A
--
9
35
mA
--
10
35
mA
--
10
35
mA
--
20
60
mA
Notes: 1. Applies to XT pin. 2. Applies to TEST pin. 3. Applies to RD and DW pins.
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ML2252/54-XXX, ML22Q54
DC Characteristics (5 V) ML2252/54-XXX
DVDD = AVDD = 4.5 to 5.5 V, DGND = AGND = 0 V, Ta = -40 to +85C Parameter "H" input voltage "L" input voltage "H" output voltage "L" output voltage "H" input current 1 "H" input current 2 (Note 1) "H" input current 3 (Note 2) "L" input current 1 "L" input current 2 (Note 3) "L" input current 3 (Note 1) Operating current consumption 1 Operating current consumption 2 Standby current consumption Symbol VIH VIL VOH VOL IIH1 IIH2 IIH3 IIL1 IIL2 IIL3 IDD1 IDD2 IDDS Condition -- -- IOH = -1 mA IOL = 2 mA VIH = VDD VIH = VDD VIH = VDD Pull-down resistor built in pin VIL = GND VIL = GND Pull-up resistor built in pin VIL = GND fOSC = 4.096 MHz at no load OPTANA = "L" fOSC = 4.096 MHz at no load OPTANA = "H" Ta = -40 to +70C Ta = -40 to +85C Min. 0.8 x VDD -- VDD -0.4 -- -- 0.8 30 -10 -230 -20 -- -- -- -- Typ. -- -- -- -- -- 5.0 -- -- -- -5.0 19 23 -- -- Max. -- 0.2 x VDD -- 0.4 10 20 350 -- -60 -0.8 40 40 15 100 Unit V V V V
A A A A A A
mA mA
A A
Notes: 1. Applies to XT pin. 2. Applies to TEST pin. 3. Applies to RD and DW pins.
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Analog Section Characteristics (3 V) ML2252/54-XXX, ML22Q54
ML2252/54-XXX: DVDD = AVDD = 2.7 to 3.6 V, DGND = AGND = 0 V, Ta = -40 to +85C ML22Q54: DVDD = AVDD = 2.7 to 3.6 V, DGND = AGND = 0 V, Ta = 0 to +70C Parameter AOUT output load resistance AOUT output voltage range DAO output impedance OUT(+), OUT(-) "H" level output voltage OUT(+), OUT(-) "L" level output voltage Analog output maximum amplitude when PWM output is selected. Symbol RLAO VAOUT RDAO VPWMH VPWML Condition -- No output load -- IOH = -2 mA IOH = 2 mA 20 kHz LPF used when OPTANA pin = "H". Min. 50 0.5 30 AVDD -0.4 -- Typ. -- -- 43 -- -- Max. -- AVDD -0.5 60 -- 0.4 AVDD x 0.5 Unit k V k V V
VPWMO
--
--
VP-P
Analog Section Characteristics (5 V) ML2252/54-XXX
DVDD = AVDD = 4.5 to 5.5 V, DGND = AGND = 0 V, Ta = -40 to +85C Parameter AOUT output load resistance AOUT output voltage range DAO output impedance OUT(+), OUT(-) "H" level output voltage OUT(+), OUT(-) "L" level output voltage Analog output maximum amplitude when PWM output is selected. Symbol RLAO VAOUT RDAO VPWMH VPWML Condition -- No output load -- IOH = -2 mA IOH = 2 mA 20 kHz LPF used when OPTANA pin = "H". Min. 50 0.5 30 AVDD -0.4 -- Typ. -- -- 43 -- -- Max. -- AVDD -0.5 60 -- 0.4 AVDD x 0.5 Unit k V k V V
VPWMO
--
--
VP-P
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FUNCTIONAL DESCRIPTION
Micro-computer Interface The micro-computer interface in the ML2250 family has 2 types of interface circuits built in: Parallel interface and serial interface. The interface setting can be changed with the SERIAL pin. SERIAL pin = "H" level: Serial interface SERIAL pin = "L" level: Parallel interface Table below shows the SERIAL pin status in the serial and parallel interfaces.
SERIAL = "L" Parallel interface D7 (I/O) D6 (I/O) D5 (I/O) D4 (I/O) D3 (I/O) D2 (I/O) D1 (I/O) D0 (I/O) Data input/output pins D (I) SCK (I) DO (O) D4 (I) D3 (I) D2 (I) D1 (I) D0 (I) SERIAL = "H" Serial interface Serial data input pin Serial clock input pin Serial data output pin Not used. (Input "L" level.) Not used. (Input "L" level.) Not used. (Input "L" level.) Not used. (Input "L" level.) Not used. (Input "L" level.)
1. Parallel Interface When selecting the parallel interface, the I/O pins CS, WR, DW, D7 to D0, and RD are used as input pins to input various commands and data, and as output pins to read out the status of the commands and data input. The micro-computer interface becomes effective when the CS pin is set to "L" level. When a command or data is input, the input data to D7 through D0 pins is captured inside the device on the rising edge of the WR pin. The DW pin is used to input data after having input the EXT or Flash I/F command. The method to input data to the DW pin is the same as the method to input command from the WR pin. To read the channels status, pins CS and RD are made "L" level. By doing so, the status signals (NCR1, NCR2, BUSY1, BUSY2) of each channel are output to D3 through D0 pins. D7 to D4 pins usually output "L" level.
Command and Data Input Timing
CS (I) WR, DW (I)
D7 to D0 (I/O)
Data Stable
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OKI Semiconductor
ML2252/54-XXX, ML22Q54
Status Read Timing
CS (I) RD (I)
D7 to D0 (I/O)
Data Stable
Table below shows the contents of each data output when reading the status of the channels.
Pin D7 D6 D5 D4 D3 D2 D1 D0 "L" level "L" level "L" level "L" level Channel 2 busy output (BUSY2) Channel 1 busy output (BUSY1) Channel 2 NCR output (NCR2) Channel 1 NCR output (NCR1) Output status signal
The BUSY signal outputs "L" level when either a command is being processed or the playback of a pertinent channel is going on. In other states, the BUSY signal outputs "H" level. The NCR signal outputs "L" level when either a command is being processed or a pertinent channel is in standby for playback. In other states, the NCR signal outputs "H" level.
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FEDL2250DIGEST-01
OKI Semiconductor
ML2252/54-XXX, ML22Q54
2. Serial Interface When selecting the serial interface, the I/O pins CS, WR, DW, DI, SCK, RD, and DO are used as input pins to input various commands and data, and as output pins to read out the status of the commands and data. The micro-computer interface becomes effective when CS pin is set to "L" level. To input the commands and data, "L" level is input to CS and WR pins followed by, from MSB, to DI pin in synchronization with the input clock signal at SCK pin. Data at DI pin is captured inside the device on the rising or falling edge of the clock at SCK pin. And the command is executed on the rising edge of the WR pin. The selection of rising/falling edge of SCK clock is determined by the input level of the SCK pin on the falling edge of the CS pin. If the SCK pin on the falling edge of the CS pin is at "L" level, the DI pin data is captured inside the device on the rising edge of SCK clock. Conversely, if the SCK pin on the falling edge of the CS pin is at "H" level, then the DI pin data is captured on the falling edge of SCK clock. Use the DW pin to input various data after having input the EXT or Flash I/F command. The data input method is the same as to input data from the WR pin.
Command and Data Input Timings * SCK Rising Edge Operation
CS (I) WR, DW (I)
DI (I)
D7 D6 D5 D4 D3 D2 D1 D0
SCK (I)
* SCK falling Edge Operation
CS (I) WR, DW (I)
DI (I)
D7 D6 D5 D4 D3 D2 D1 D0
SCK (I)
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FEDL2250DIGEST-01
OKI Semiconductor
ML2252/54-XXX, ML22Q54
To read the channel status, input "L" level to CS and RD pins. DQ pin will output the channel status in synchronization with SCK clock. The selection of rising/falling edge of SCK clock, similar to when inputting the commands and data, is determined by the level at SCK pin at the falling edge of CS pin. The status signals in the parallel interface are output to D7 to D0 pins sequentially from D7. Status Read Timing * SCK Rising Edge Operation
CS (I) RD (I)
SCK (I) Hi-Z Hi-Z
DO (O)
D7 D6 D5 D4 D3 D2 D1 D0
* SCK Falling Edge Operation
CS (I) RD (I)
SCK (I) Hi-Z Hi-Z
DO (O)
D7 D6 D5 D4 D3 D2 D1 D0
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FEDL2250DIGEST-01
OKI Semiconductor
ML2252/54-XXX, ML22Q54
Commands List Each command is 1-byte (8 bits) input. PLAY, MUON, and FLASH I/F only are 2 bytes input.
Command PUP1 PUP2 PDWN1 D7 0 0 0 D6 0 0 0 D5 0 0 1 D4 0 1 0 D3 0 0 0 D2 0 0 0 D1 0 0 0 D0 0 0 0 Description Instantly shifts the power down device to the command standby state. Suppresses pop noise and shifts the power down device to the command standby state. Instantly shifts the device from the command standby state to the power down state. Suppresses pop noise and shifts the device from the command standby state to power down state. Inputs the phrase after the playback channel is specified, and then starts the playback. Playback start command with phrase specification. Inputs the phrase after the playback channel is specified, and then starts the playback. Playback start command without phrase specification. Inputs the phrase with the FADR command and starts the playback on multiple channels at the same time. Phrase specification command. With this command, specifies the playback phrase for each channel. Specifies the finish channel and ends the voice. Inserts silence time after specifying the channel to insert silence, and then inserts silence. Repeats the playback mode setting command. Effective only for the channel being used for playback. Repeat playback mode releasing command. Inputting the STOP command releases repeat playback mode automatically. Specifies the channel whose sound volume is to be set, and then sets the volume of that channel. Inputs voice data from the CPU I/F to play it back. Performs data read/write/erase of the built-in flash memory. This command cannot be used while the playback is going on. (Applicable to the ML22Q54.)
PDWN2
0 0 F7
0 1 F6
1 0 F5
1 0 F4
0 0 F3
0 0 F2
0 C1 F1
0 C0 F0
PLAY
START
0
1
0
1
0
0
C1
C0
FADR STOP MUON SLOOP
0 M7 0 1 M7 1
1 M6 1 0 M6 0
1 M5 1 0 M5 0
0 M4 1 0 M4 1
0 M3 0 0 M3 0
0 M2 0 0 M2 0
C1 M1 C1 C1 M1 C1
C0 M0 C0 C0 M0 C0
CLOOP VOL EXT
1 1 V7 1
0 0 V6 1
1 1 V5 0
0 1 V4 0
0 0 V3 0
0 0 V2 0
C1 C1 V1 0
C0 C2 V0 0
Flash I/F
1
1
0
1
BE
SE
WR
RD
C1, C0:
Channel specification (C0 = "1": Channel 1; CH = "1": Channel 2; C0, C1 = "1": Channel 1, Channel 2) F7 to F0: Phrase address M7 to M0: Silence time length X0: Releases the repeated playback V4 to V0: Sound volume RD, WR, SE, BE: Mode (RD = "1": Read data; WR = "1": Write data; SE = "1": Erase sector; BE = "1": Erase block)
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Power Down Function In power down state, the power down function in the device stops the internal operation and oscillation, sets AOUT to GND, and minimizes the static Idd. When an external clock is in use, input "L" level to the XT pin, so that current does not flow into the oscillation circuit. Figure below shows the equivalent circuit of XT and XT pins.
To master clock inside the device 1 M approx.
RESET
XT
XT
Channel Status Channel status is of 2 types: NCRn and BUSYn.
Channel CH1 CH2 Channel status NCR1 NCR2
BUSY1 BUSY2
NCRn = "H" indicates that it is possible to input the PLAY, START and MUON commands for the phrase to be played back next for channel n. BUSYn = "H" indicates a state in which channel n has not performed voice processing. BUSYn = "L" indicates a state in which channel n is performing voice processing. Meanwhile, after a command is input, the NCR and BUSY signals of all channels are at "L" level during the processing of the command.
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FEDL2250DIGEST-01
OKI Semiconductor
ML2252/54-XXX, ML22Q54
Voice Synthesis Algorithm The ML2250 family contains 5 algorithm types to match the characteristic of playback voice: 2-bit ADPCM 2 algorithm, 4-bit ADPCM 2 algorithm, 8-bit PCM algorithm, 8-bit non-linear PCM algorithm, and 16-bit PCM algorithm. Key feature of each algorithm is described in the table below.
Voice synthesis algorithm Oki 2-bit ADPCM2 Applied waveform Normal voice waveform Feature Oki's specific speech synthesis algorithm of low bit rate with improved 2-bit ADPCM. Oki's specific speech synthesis algorithm of improved waveform follow-up with improved 4-bit ADPCM. Algorithm which plays back mid-range of waveform as 10-bit equivalent voice quality. Normal 8-bit PCM algorithm Normal 16-bit PCM algorithm
Oki 4-bit ADPCM2
Normal voice waveform High-frequency components inclusive sound effect etc. High-frequency components inclusive sound effect etc. High-frequency components inclusive sound effect etc.
Oki 8-bit Nonlinear PCM 8-bit PCM 16-bit PCM
Memory Allocation and Creating Voice Data The ROM is partitioned into 4 data areas: voice (i.e., phrase) control area, test area, voice area, and phrase control table area. The voice control area manages the ROM's voice data. It controls the start/end addresses of voice data, usage/not usage of the phrase control table function and so on. The voice control area stores voice control data for 256 phrases. The test area stores the data for testing. The voice area stores the actual waveform data. The phrase control table area stores data for effective use of voice data. As for the details, please refer to the Phrase Control Table Function. There is no phrase control table area if the phrase control table is not used. The ROM data is created using a development tool.
ROM Addresses (ML2252) 0x00000 0x007FF 0x00800 0x00807 0x00808 Voice area Test area Voice control area (16 Kbit Fixed)
max: 0x1FFFF Phrase Control Table area Depends on creation of ROM data.
max: 0x1FFFF
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OKI Semiconductor
ML2252/54-XXX, ML22Q54
Built-in ROM Usage Prohibited Area (Applies to ML2252/54-XXX, ML22Q54) The 8 bytes between the voice control area and the voice area in the ROM is the prohibited area for use. The voice data are stored automatically behind 00808(HEX) address by using the development tool (AR762, AR203, AR204) when creating the ROM data. Table below lists the addresses prohibited for use in every ROM model.
Model ML2252 ML2254, 22Q54 Voice data area 00808 to 1FFFF 00808 to 7FFFF Usage prohibited area 00800 to 00807 00800 to 00807
Note: The addresses are indicated in hexadecimal notation.
Playback Time and Memory Capacity The playback time depends upon the memory capacity, sampling frequency, and playback method. The equation showing the relationship is given below. 1.024 x (Memory capacity - 16) (Kbit) Playback time [sec] = Sampling frequency (kHz) x Bit length (Bit length is ADPCM, ADPCM 2 = 4 bits; PCM = 8 bits.) Example: Let the sampling frequency be 16 kHz and 4-bit ADPCM algorithm. If one 8 Mbits ROM is used, then the playback time is obtained as follows: 1.024 x (8192 - 16) (Kbit) 16 (kHz) x 4 (bit) 131 (sec)
Playback time =
The above equation gives the playback time when the phrase control table function is not used.
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OKI Semiconductor
ML2252/54-XXX, ML22Q54
Mixing Function The ML2250 family can perform simultaneous mixing of 2 channels. It is possible to specify PLAY and STOP for each channel separately. * Precautions for Waveform Clamp at the Time of Channels Mixing When mixing of channels is done, the clamp occurrence possibility increases from the mixing calculation point of view. If it is known beforehand that the clamp will occur, then adjust the sound volume by VOL command. * Mixing of Different Sampling Frequency It is not possible to perform analog mixing by a different sampling frequency. When performing analog mixing, the sampling frequency group of the first playback channel is selected. Therefore, please note that if analog mixing is performed by a sampling frequency group other than the selected sampling frequency group, then the playback will not be of constant speed: some times faster and at other times slower. The available sampling groups for analog mixing by a different sampling frequency are listed below. 4.0 kHz, 8.0 kHz, 16.0 kHz, 32.0 kHz *** (Group 1) 5.3 kHz, 10.6 kHz, 21.3 kHz, 42.7 kHz *** (Group 2) 6.4 kHz, 12.8 kHz, 25.6 kHz *** (Group 3) Figures below show a case when a sampling frequency group played back a different sampling frequency group.
fs = 16.0 kHz Channel 1 fs = 25.6 kHz (Invalid. Played back as fs = 32.0 kHz.) Channel 2
Figure 1 In Case a Different Sampling Frequency Played Back during Playback of the Other Channel Playback
fs = 16.0 kHz Channel 1
Normal playback if not played back by other channel.
fs = 25.6 kHz (Valid) Channel 2 End of channel 1
Figure 2 In Case a Different Sampling Frequency Played Back after the End of the Other Channel
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FEDL2250DIGEST-01
OKI Semiconductor
ML2252/54-XXX, ML22Q54
Phrase Control Table Function The phrase control table function makes it possible to play back multiple phrases in succession. The following functions are set using the phrase control table function: * Continuous playback: There is no limit to the number of times a continuous playback can be specified. It depends on the memory capacity only. * Silence insertion function: 4 to 1024 ms Using the phrase control table function enables to effectively use the memory capacity of voice ROM. Below is an example of the ROM configuration in the case of using the phrase control table function.
Example 1: Phrases Using the Phrase Control Table Function
Phrase 1 Phrase 2 Phrase 3 Phrase 4 Phrase 5
A A E E A B C
B C D D B
D D
D
Silence
E
C
D
Example 2: Example of ROM Data in case Example 1 Converted to ROM
Address control area A B D E F Editing area C
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FEDL2250DIGEST-01
OKI Semiconductor
ML2252/54-XXX, ML22Q54
Converting PWM Signal to Analog Signal Examples of circuits that convert the PWM output signal to an Analog signal when PWM output is selected (OPTANA pin = "H") are given below. 1. Example Using Active LPF The LPF primary side is configured as below using an OP amplifier.
ML2250f C1 R2 R1 OUT(+) R1 OUT(-) R2 + Speaker amplifier C1 R3 -
C2
R3
LPC cutoff frequency, fC, is determined by fC =
1 2R2C1
Ratio of resistors R1 to R2 determines the voltage amplification factor. To set the amplification factor 2 times of the OP amplifier, set R1:R2 = 1:2. 2. Example Using LC Filter Secondary LPF is configured using a coil (L) and a capacitor (C). This configuration can directly drive a speaker. However, a buffer is required between the PWM output and the LC filter.
ML2250f OUT(+) L C OUT(-) L C
LPF cutoff frequency, fC, is determined by fC =
1 . 2 LC
In the case of secondary Butterworth type LC filter, the constants are obtained by the following equations: 1 1 L = 1.4142 x C= 2fC 1.412 x RL x (2fC) Here, RL stands for the output load resistance and fC stands for cutoff frequency of LC filter.
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OKI Semiconductor
ML2252/54-XXX, ML22Q54
APPLICATION CIRCUIT EXAMPLE (ML2252/54-XXX, ML22Q54)
MCU RESET CS WR RD D7-0 8 NCR1 NCR2 BUSY1 BUSY2 SERIAL OPTANA AOUT Speaker amplifier
30 pF XT 4.096 MHz XT 30 pF
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FEDL2250DIGEST-01
OKI Semiconductor
ML2252/54-XXX, ML22Q54
PACKAGE DIMENSIONS
(Unit: mm)
QFP44-P-910-0.80-2K
Mirror finish
5
Notes for Mounting the Surface Mount Type Package
Package material Lead frame material Pin treatment Package weight (g) Rev. No./Last Revised
Epoxy resin 42 alloy Solder plating (5m) 0.41 TYP. 4/Nov. 28, 1996
The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
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FEDL2250DIGEST-01
OKI Semiconductor
ML2252/54-XXX, ML22Q54
REVISION HISTORY
Document No. FEDL2250DIGEST-01 Page Date Previous Edition - Current Edition - Final edition 1 Description
Oct. 15, 2002
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FEDL2250DIGEST-01
OKI Semiconductor
ML2252/54-XXX, ML22Q54
NOTICE 1. The information contained herein can change without notice owing to product and/or technical improvements. Before using the product, please make sure that the information being referred to is up-to-date. 2. The outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. When planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. When designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. Neither indemnity against nor license of a third party's industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. No responsibility is assumed by us for any infringement of a third party's right which may result from the use thereof. The products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). These products are not authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. Certain products in this document may need government approval before they can be exported to particular countries. The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. No part of the contents contained herein may be reprinted or reproduced without our prior permission. Copyright 2002 Oki Electric Industry Co., Ltd.
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